DFU activation 후 App 부팅 시 전원 OFF 처리 추가

components/libraries/bootloader/nrf_bootloader.c

@@ -64,6 +64,7 @@ static volatile bool m_flash_write_done;
 
 #define SCHED_QUEUE_SIZE      32          /**< Maximum number of events in the scheduler queue. */
 #define SCHED_EVENT_DATA_SIZE NRF_DFU_SCHED_EVENT_DATA_SIZE /**< Maximum app_scheduler event size. */
+#define POST_DFU_APP_BOOT_GPREGRET2_MASK 0x02U
 
 #if !(defined(NRF_BL_DFU_ENTER_METHOD_BUTTON)    && \
       defined(NRF_BL_DFU_ENTER_METHOD_PINRESET)  && \
@@ -470,6 +471,7 @@ ret_code_t nrf_bootloader_init(nrf_dfu_observer_t observer)
             break;
 
         case ACTIVATION_SUCCESS:
+            nrf_power_gpregret2_set(nrf_power_gpregret2_get() | POST_DFU_APP_BOOT_GPREGRET2_MASK);
             bootloader_reset(true);
             NRF_LOG_ERROR("Unreachable");
             return NRF_ERROR_INTERNAL; // Should not reach this.

project/ble_peripheral/ble_app_bladder_patch/main.c

@@ -181,6 +181,7 @@
 #define POWER_OFF_DELAY                 3000        /* Power-off delay: 3s after LED indication */
 #define POWER_RESET_DELAY               2000        /* Reset delay: 2s */
 #define LED_NUM                         24          /* LED pin number */
+#define POST_DFU_APP_BOOT_GPREGRET2_MASK 0x02U       /* Bootloader marker after DFU activation */
 
 /*==============================================================================
  * BLE Instances (statically allocated via SoftDevice macros)
@@ -2182,6 +2183,17 @@ int main(void)
      *────────────────────────────────────────────────────────────*/
     power_hold_init();
 
+    if ((NRF_POWER->GPREGRET2 & POST_DFU_APP_BOOT_GPREGRET2_MASK) != 0)
+    {
+        NRF_POWER->GPREGRET2 &= ~POST_DFU_APP_BOOT_GPREGRET2_MASK;
+        NRF_P0->OUTCLR = (1UL << 8);
+        NRF_P0->DIRSET = (1UL << 8);
+        while (true)
+        {
+            __WFE();
+        }
+    }
+
     if (power_off_duble_prohibit)
     {
         return 0;

project/ble_peripheral/ble_app_bladder_patch/pca10056/s140/arm5_no_packs/RTE/Device/nRF52840_xxAA/system_nrf52.c

@@ -32,6 +32,8 @@ NOTICE: This file has been modified by Nordic Semiconductor ASA.
 #include "system_nrf52_approtect.h"
 
 #define __SYSTEM_CLOCK_64M      (64000000UL)
+#define POWER_HOLD_PIN          8UL
+#define POWER_HOLD_PIN_MASK     (1UL << POWER_HOLD_PIN)
 
 
 #if defined ( __CC_ARM )
@@ -89,6 +91,15 @@ void SystemCoreClockUpdate(void)
 
 void SystemInit(void)
 {
+    /* Keep the external power latch asserted immediately after reset. */
+    NRF_P0->OUTSET = POWER_HOLD_PIN_MASK;
+    NRF_P0->DIRSET = POWER_HOLD_PIN_MASK;
+    NRF_P0->PIN_CNF[POWER_HOLD_PIN] =
+        (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos) |
+        (GPIO_PIN_CNF_INPUT_Disconnect << GPIO_PIN_CNF_INPUT_Pos) |
+        (GPIO_PIN_CNF_PULL_Disabled << GPIO_PIN_CNF_PULL_Pos) |
+        (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) |
+        (GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos);
     /* Enable SWO trace functionality. If ENABLE_SWO is not defined, SWO pin will be used as GPIO (see Product
        Specification to see which one). */
     #if defined (ENABLE_SWO) && defined(CLOCK_TRACECONFIG_TRACEMUX_Pos)

project/dfu/secure_bootloader/main.c

@@ -76,6 +76,8 @@ static void dfu_observer(nrf_dfu_evt_type_t evt_type)
             break;
         case NRF_DFU_EVT_DFU_STARTED:
             break;
+        case NRF_DFU_EVT_DFU_COMPLETED:
+            break;
         default:
             break;
     }

project/dfu/secure_bootloader/pca10056_s140_ble/arm5_no_packs/RTE/Device/nRF52840_xxAA/system_nrf52.c

@@ -32,6 +32,8 @@ NOTICE: This file has been modified by Nordic Semiconductor ASA.
 #include "system_nrf52_approtect.h"
 
 #define __SYSTEM_CLOCK_64M      (64000000UL)
+#define POWER_HOLD_PIN          8UL
+#define POWER_HOLD_PIN_MASK     (1UL << POWER_HOLD_PIN)
 
 
 #if defined ( __CC_ARM )
@@ -89,6 +91,15 @@ void SystemCoreClockUpdate(void)
 
 void SystemInit(void)
 {
+    /* Keep the external power latch asserted immediately after reset. */
+    NRF_P0->OUTSET = POWER_HOLD_PIN_MASK;
+    NRF_P0->DIRSET = POWER_HOLD_PIN_MASK;
+    NRF_P0->PIN_CNF[POWER_HOLD_PIN] =
+        (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos) |
+        (GPIO_PIN_CNF_INPUT_Disconnect << GPIO_PIN_CNF_INPUT_Pos) |
+        (GPIO_PIN_CNF_PULL_Disabled << GPIO_PIN_CNF_PULL_Pos) |
+        (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) |
+        (GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos);
     /* Enable SWO trace functionality. If ENABLE_SWO is not defined, SWO pin will be used as GPIO (see Product
        Specification to see which one). */
     #if defined (ENABLE_SWO) && defined(CLOCK_TRACECONFIG_TRACEMUX_Pos)

project/dfu/secure_bootloader/pca10056_s140_ble/arm5_no_packs/secure_bootloader_ble_s140_pca10056.uvoptx

@@ -73,7 +73,7 @@
         <LExpSel>0</LExpSel>
       </OPTXL>
       <OPTFL>
-        <tvExp>0</tvExp>
+        <tvExp>1</tvExp>
         <tvExpOptDlg>0</tvExpOptDlg>
         <IsCurrentTarget>1</IsCurrentTarget>
       </OPTFL>